module tb_core ();

reg         clock;
reg         reset;

//initial begin
//    $fsdbDumpfile("run.fsdb");
//    $fsdbDumpvars(0, top);
//end

wire    [31:0]      maddr;
wire                wenable;
wire    [31:0]      wdata;
wire                renable;
wire    [31:0]      rdata;
wire                m_ok;
wire    [31:0]      iaddr;
wire    [31:0]      instr;
wire                i_ok;
wire    [2:0]       stat;

    core U_cpu(
        .clk  (clock  ),
        .rst_n  (~reset  ),
        .maddr  (maddr  ),
        .wenable(wenable),
        .wdata  (wdata  ),
        .renable(renable),
        .rdata  (rdata  ),
        .m_ok   (m_ok   ),
        .pc     (iaddr  ),
        .instr  (instr  ),
        .i_ok   (i_ok   ),
        .stat   (stat   )
    );

    bmemory U_mem(
        .maddr  (maddr  ),
        .wenable(wenable),
        .wdata  (wdata  ),
        .renable(renable),
        .rdata  (rdata  ),
        .m_ok   (m_ok   ),
        .iaddr  (iaddr  ),
        .instr  (instr  ),
        .i_ok   (i_ok   ),
        .clock  (clock  )
    );

    Check U_Check();

endmodule

